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Lecture Details :
The GPU architecture is characterized by memory access bandwidth that, although fast, is often limiting in comparison to compute throughput. Thus, achieving performance critically depends on finding ways to reduce and regularize global memory access. Three important algorithmic strategies for conserving bandwidth are “register/memory tiling”, “layout transformation” and “thread coarsening”. These come at a cost of increased on-chip memory usage, which is also a limited resource. We will discuss a variety of examples from PDE solvers, linear algebra, and convolution.
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