Digital System design with PLDs and FPGAs

Overview

Revision of basic Digital systems - Combinational Circuits - Sequential Circuits - Timing- Electrical Characteristics - Power Dissipation,Current state of the field:SoC, IP Design, SoPC - Design methodology, System Modeling, Hardware-Software Co-design - Device Technology - Application Domains,Digital system Design:Top down Approach to Design, Case study - Data Path, Control Path - Controller behavior and Design - Case study Mealy & Moore Machines - Timing of sequential circuits - Pipelining, Resource sharing - FSM issues (Starring state, Power on Reset, State diagram optimization, State Assignment,Asynchronous Inputs, Output Races, fault Tolerance ...) - VHDL for Synthesis:Introduction - Behavioral, Data flow, Structural Models - Simulation Cycles - Process - Concurrent Statements - Sequential Statements - Loops - Delay Models - Sequential Circuits, FSM Coding - Library, Packages - Functions, Procedures - Operator Inferencing - Test bench,

Programmable Logic Devices:Evolution: PROM, PLA, PAL - Architecture of PAL's - Applications - Programming PLD's - Design Flow - Programmable Interconnections - Complex PLD's (MAX - 7000, APEX) - Architecture, Resources - Applications - Tools - Demonstration of the tool,DFPGA's : Introduction - Logic Block Architecture - Routing Architecture - Programmable Interconnections - Design Flow - Xilinx Virtex-II (Architecture) - Altera Stratix, Actel 54SX Architecture - Boundary Scan - Programming FPGA's - Constraint Editor, Static Timing Analysis - One hot encoding - Applications - Tools - Case Study - Xilinx Virtex II Pro, Embedded System on Programmable Chip - Hardware-software co-simulation, Bus function models, BFM Simulation - Debugging FPGA Design, Chipscope Pro.