Advanced Logic Synthesis

Other Course , Prof. Dhiraj Taneja

Lecture 1: MOS Transistor

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Lecture Details :

Advanced Logic Synthesis by Dhiraj Taneja,Broadcom, Hyderabad.For more details on NPTEL visit

Course Description :

MOS Transistor:Mos Transistor, Logic, Pmos Transistor, Nmos Transistor, CMOS Transistor, Design of basic gates, combinational circuits and sequential circuits using MOS transistor logic. Stick diagrams and layout diagrams for basic circuits, Lambda Based Rules, Calculation of propagation delays;Digital timing in CMOS:Static CMOS circuit, NMOS Transistors in Series/Parallel Connection, PMOS Transistors in Series/Parallel Connection, Complex CMOS Gate, Cell Design, Standard Cells, Stick Diagrams, Switch Delay Model, Fast Complex Gates, Sizing Logic Paths for Speed, Logical Effort of Gates, Multistage Networks, Ratioed Logic, Pseudo-NMOS - Sequential logic, Latch versus register, Latch-Based Design, Maximum Clock Frequency, Meta-Stability, Mux-Based Latches, Master-Slave (Edge-Triggered) Register, Setup/Hold Times - Wire Load Model. Linear timing model. Non linear delay model (NLDM). Timing models for combinational & sequencial cells - Clock specification, Basic clock specification. Extended clock specification. Clock uncertainty. Inter-clock uncertainty. Master clock latency. Generated clocks. Divided clock. Multiplied clock. Gated clock. Master clock at clock gating cell output. Edge_shift option. Generated clock latency

Process Of Synthesis, Libraries And Technology Mapping:Introduction to synthesis, synthesizable and non synthesizable constructs. Logical synthesis of basic - combinational and sequential circuits.Synthesis Methodologies. Pre and post synthesis mismatch. Translation, mapping and optimization. Overview of Libraries: Target library, synthetic library, symbol library and link Library. Reading the design. Design constraints: design rule constraints and optimization constraints. Optimization for power, timing and area. Compile strategies in synthesis. Design analysis. Importance of wire load models. Specifying operating conditions and system interface characteristics - Advanced Synthesis flow:Post synthesis flow and analysis. Advanced critical path resynthesis, grouping and ungrouping the designs, cost priorities, optimization with timing and area efforts. Register retiming. Incremental, power and dft flows in synthesis - Timing Analysis:Introduction to timing concepts. Setup and hold times. Setup and hold time equalities and inequalities. Timing paths. Static timing delay calculation for basic flip flop & sequential circuits. Definition of timing path. Grouped timing paths. Timing path delay. Recovery and removal times. Pulse width, signal slew. Clock latency. Clock skew. Input arrival time. Output required time. Slack and critical path. False paths. Multi-cycle paths

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