High Performance Computer Architecture

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Review of Basic Organization and Architectural Techniques:
RISC processors,Characteristics of RISC processors,RISC Vs CISC,Classification of Instruction Set Architectures,Review of performance measurements,Basic parallel processing techniques: instruction level, thread level and process level,Classification of parallel architectures.

Instruction Level Parallelism:
Basic concepts of pipelining,Arithmetic pipelines,Instruction pipelines,Hazards in a pipeline: structural, data, and control hazards,Overview of hazard resolution techniques,Dynamic instruction scheduling,Branch prediction techniques,Instruction-level parallelism using software approaches,Superscalar techniques,Speculative execution,Review of modern processors /*The objective is to explain how ILP
techniques have been deployed in modern processors*/,Pentium Processor: IA 32 and P6 microarchitectures,ARM Processor.

Memory Hierarchies:
Basic concept of hierarchical memory organization,Main memories,Cache memory design and implementation,Virtual memory design and implementation,Secondary memory technology,RAID.

Peripheral Devices:
Bus structures and standards,Synchronous and asynchronous buses,Types and uses of storage devices,Interfacing I/O to the rest of the system,Reliability and availability,I/O system design,Platform architecture.

Thread Level Parallelism:
Centralized vs. distributed shared memory,Interconnection topologies,Multiprocessor architecture,Symmetric multiprocessors,Cache coherence problem,Synchronization,Memory consistency,Multicore architecture,Review of modern multiprocessors.

Process Level Parallelism:
Distributed computers,Clusters,Grid,Mainframe computers.

Course Curriculum

Mod-21 Lec-30 Virtual Memory (Contd.) Details 55:29
Mod-12 Lec-15 Control Hazards Details 54:52
Mod-11 Lec-14 Dynamic Instruction Scheduling (Contd.) Details 57:40
Mod-21 Lec-29 Virtual Memory Details 56:5
Mod-11 Lec-13 Dynamic Instruction Scheduling Details 57:11
Mod-20 Lec-28 Main Memory Optimizations Details 54:26
Mod-29 Lec-41 Cluster, Grid and Cloud Computing Details 55:53
Mod-18 Lec-26 Cache Optimization Techniques (Contd.) Details 54:50
Mod-10 Lec-12 In Quest of Higher ILP (Contd.) Details 57:50
Mod-28 Lec-40 Distributed Memory Multiprocessors Details 54:45
Mod-18 Lec-25 Cache Optimization Techniques (Contd.) Details 56:6
Mod-10 Lec-11 In Quest of Higher ILP Details 58:6
Mod-27 Lec-39 Symmetric Multiprocessors Details 57:16
Mod-17 Lec-24 Hierarchical Memory Organization (Contd.) Details 58:36
Mod-09 Lec-10 Software Pipelining Details 45:50
Mod-26 Lec-38 Simultanoues Multithreading Details 55:25
Mod-08 Lec-09 Data Hazards Details 0:51
Mod-17 Lec-23 Hierarchical Memory Organization (Contd.) Details 59:44
Mod-25 Lec-37 Multithreading and Multiprocessing Details 54:26
Mod-07 Lec-08 Pipeline Hazards Details 55:21
Mod-17 Lec-22 Hierarchical Memory Organization (Contd.) Details 56:20
Mod-24 Lec-36 Case Studies (Contd.) Details 56:54
Mod-06 Lec-07 Instruction Pipelining Details 57:21
Mod-17 Lec-21 Hierarchical Memory Organization Details 56:50
Mod-24 Lec-35 Case Studies (Contd.) Details 48:52
Mod-05 Lec-06 Pipelining Introduction Details 56:48
Mod-16 Lec-20 Tutorial – I Details 52:24
Mod-04 Lec-05 MIPS ISA Processor (Contd.) Details 52:3
Mod-15 Lec-19 Hardware Based Speculation Details 59:38
Mod-24 Lec-34 Case Studies Details 58:9
Mod-04 Lec-04 MIPS ISA Processor Details 52:5
Mod-14 Lec-18 Dynamic Instruction Scheduling with Branch Prediction Details 54:6
Mod-23 Lec-33 Storage Technology (Contd.) Details 54:16
Mod-03 Lec-03 Instruction Set Architecture Details 56:34
Mod-13 Lec-17 Branch Prediction (Contd.) Details 57:23
Mod-23 Lec-32 Storage Technology Details 56:31
Mod-02 Lec-02 Performance Details 55:33
Mod-22 Lec-31 Virtual Machines Details 57:8
Mod-13 Lec-16 Branch Prediction Details 55:25
Mod-01 Lec-01 Introduction and Course Outline Details 54:58
Mod-19 Lec-27 High Performance Computer Architecture Details 59:23

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