This course covers the analysis and design of CMOS Analog-to-Digital and Digital-to-Analog Converters,with about 7 design assigments. The syllabus is as follows :

(i) Introduction to A/D and D/A conversion : sampling, quantization, quantization noise, aliasing and reconstruction filtering.

(ii) ADC/DAC metrics : Differential and Integral Nonlinearity, SNR, SNDR, SFDR and dynamic range.

(iii) ADC Architectures : Will cover two of these architectures in detail
(a) Flash and Floding ADCs.
(b) Oversampling Converters.
(c) Successive Approximation Converters.

(iv) DAC Design :
(a) Current steering DACs.

Other Resources

Course Curriculum

Introduction to Data Conversion Details 1:25:33
Sampling-1 Details 1:8:10
Sampling-2 Details 55:55
Nonidealities in Samples Details 54:19
Noise due to Sampling Details 57:58
Distortion in a Sampling Switch Details 59:51
Gate Boosted Switches-1 Details 52:25
Gate Boosted Switches-2 Details 55:6
Charge Injection Details 52:47
S/H Characterization – 1 Details 51:29
S/H Characterization – 2 Details 55:27
FFTs and Leakage Details 51:8
Spectral Windows – 1 Details 51:19
Spectral Windows-2 Details 54:21
ADC/DAC Definitions Details 49:57
Quantization Noise – I Details 51:25
Quantization Noise -2 Details 57:58
Oversampling & Noise Shaping Details 53:45
Delta-Sigma Modulation – 1 Details 53:27
Delta-Sigma Modulation – 2 Details 53:52
Linearized Analysis Details 58:26
Stability of Delta Sigma Modulators Details 51:58
High Order DSMs Details 52:27
NTF Design and Tradeoffs Details
Single bit Modulators Details 50:10
Loop Filter Architectures Details
Continous-time Delta Sigma Modulation Details 54:19
Implicit Antialiasing Details 53:38
Modulators with NRZ and Impulsive DACs Details 55:25
High Order CTDSMs Details 50:21
CTDM Design Details 50:9
Excess Loop Delay (ELD) Details 48:52
ELD Compensation Details 52:51
Effect of Clock Jitter on CTDSMs – 1 Details 49:54
Effect of Clock Jitter on CTDSMs – 2 Details 52:25
Dynamic Range Scaling Details 52:39
Simulation of CTDSMs Details 52:17
Integrator Design-1 Details 54:59
Integrator Design-2 Details 1:1:10
Flash ADC Design Details 50:11
Latches and Metastability Details 56:19
Offset in a Latch-1 Details 0:51
Offset in a Latch-2 Auto Zeroing Details 54:7
Auto Zeroing-2 Details 56:48
Auto Zeroing-3 Details 53:8
Autozeroing in Flash ADCs Details 57:34
Flash ADC Case Study Details 56:43
Flash ADC Case Study Details 1:4:22
Flash ADC in a Delta Sigma Loop Details 49:15
DAC Basics Details 0:53

This course is part of NPTEL online courses, delivered by IIT Madras.

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