FPGA Verilog student projects

Lecture Details

httppeople.ece.cornell.edulandcoursesece5760FinalProjectsf2009csm44_jck46index.html
This project is a velocity sensitive hardware based piano synth. We simulated two strings per note using a Karplus Strong algorithm written in Verilog, and coupled it with a Casio electric piano keyboard fitted with custom switches to act as a user interface. On an Altera DE2 board we built a hardware Karplus-Strong synthesizer to simulate a piano key with two strings, along with a hardware timer. The timer was used to determine the key pushs velocity, which in turn affected the volume level of the synthesized sound. The keyboard fed into the DE2 using the boards GPIO ports.