FPGA Verilog student projects
Cornell University, , Prof. Bruce Land
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Updated On 02 Feb, 19
4.1 ( 11 )
This project is a velocity sensitive hardware based piano synth. We simulated two strings per note using a Karplus Strong algorithm written in Verilog, and coupled it with a Casio electric piano keyboard fitted with custom switches to act as a user interface. On an Altera DE2 board we built a hardware Karplus-Strong synthesizer to simulate a piano key with two strings, along with a hardware timer. The timer was used to determine the key pushs velocity, which in turn affected the volume level of the synthesized sound. The keyboard fed into the DE2 using the boards GPIO ports.
Sep 12, 2018
Excellent course helped me understand topic that i couldn't while attendinfg my college.
March 29, 2019
Great course. Thank you very much.