Digital System design with PLDs and FPGAs

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2 STUDENTS

Revision of basic Digital systems – Combinational Circuits – Sequential Circuits – Timing- Electrical Characteristics – Power Dissipation,Current state of the field:SoC, IP Design, SoPC – Design methodology, System Modeling, Hardware-Software Co-design – Device Technology – Application Domains,Digital system Design:Top down Approach to Design, Case study – Data Path, Control Path – Controller behavior and Design – Case study Mealy & Moore Machines – Timing of sequential circuits – Pipelining, Resource sharing – FSM issues (Starring state, Power on Reset, State diagram optimization, State Assignment,Asynchronous Inputs, Output Races, fault Tolerance …) – VHDL for Synthesis:Introduction – Behavioral, Data flow, Structural Models – Simulation Cycles – Process – Concurrent Statements – Sequential Statements – Loops – Delay Models – Sequential Circuits, FSM Coding – Library, Packages – Functions, Procedures – Operator Inferencing – Test bench,

Programmable Logic Devices:Evolution: PROM, PLA, PAL – Architecture of PAL’s – Applications – Programming PLD’s – Design Flow – Programmable Interconnections – Complex PLD’s (MAX – 7000, APEX) – Architecture, Resources – Applications – Tools – Demonstration of the tool,DFPGA’s : Introduction – Logic Block Architecture – Routing Architecture – Programmable Interconnections – Design Flow – Xilinx Virtex-II (Architecture) – Altera Stratix, Actel 54SX Architecture – Boundary Scan – Programming FPGA’s – Constraint Editor, Static Timing Analysis – One hot encoding – Applications – Tools – Case Study – Xilinx Virtex II Pro, Embedded System on Programmable Chip – Hardware-software co-simulation, Bus function models, BFM Simulation – Debugging FPGA Design, Chipscope Pro.

Course Curriculum

Course Contents, Objective Details 57:34
Revision of Prerequisite Details 59:34
Design of Synchronous Sequential Circuits Details 52:35
Analysis of Synchronous Sequential Circuits Details 57:18
Top-down Design Details 57:54
Controller Design Details 58:40
Control algorithm and State diagram Details 56:49
Case study 1 Details 58:24
Entity, Architecture and Operators Details 58:16
Concurrency, Data flow and Behavioural models Details 57:22
Structural Model, Simulation Details 59:14
Simulating Concurrency Details 59:6
Classes and Data types Details 57:38
Concurrent statements and Sequential statements Details 57:56
Sequential statements and Loops Details 59:29
Modelling flip-flops, Registers Details 57:14
Synthesis of Sequential circuits Details 57:59
Libraries and Packages Details 56:54
Operators, Delay modelling Details 57:28
Delay modelling Details 58:44
VHDL Examples Details 58:22
VHDL Examples, FSM Clock Details 0:59
FSM issues 1 Details 52:16
FSM Issues 2 Details 57:51
FSM Issues 3 Details 58:7
VHDL coding of FSM Details 58:43
FSM Issues 4 Details 59:12
FSM Issues 5 Details 58:11
Synchronization 1 Details 59:3
Synchronization 2 Details 58:15
Evolution of PLDs Details 58:38
Simple PLDs Details 59:17
Simple PLDs: Fitting Details 59:11
Complex PLDs Details 58:24
FPGA Introduction Details 58:29
FPGA Interconnection, Design Methodology Details 58:20
Xilinx Virtex FPGA’s CLB Details 58:51
Xilinx Virtex Resource Mapping, IO Block Details 58:44
Xilinx Virtex Clock Tree Details 57:47
FPGA Configuration Details 58:30
Altera and Actel FPGAs Details 58:42
VHDL Test bench Details 58:34
Case study 2 Details 58:5
Case study on FPGA Board Details 57:19

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