Computer Architecture II

Other Course , Spring 2013 , Prof. Onur Mutlu

605 students enrolled

Overview

Introduction and Basics - Fundamental Concepts and ISA - ISA Tradeoffs - More ISA Tradeoffs - ISA Wrap-Up, Single-Cycle- Multi-Cycle Microarchitecture - Microprogramming - Pipelining - Data Dependence Handling - Control Dependence Handling - Branch Prediction - Predication and Exceptions - State Maintenance & Recovery - Out-of-Order Execution - Data Flow and SIMD - Virtual Memory - SIMD and GPUs - GPUs, VLIW, Systolic Arrays - Static Instruction Scheduling - Memory Hierarchy - Caches - Advanced Caches - Main Memory and DRAM Basics - Memory Controllers & Scheduling - Memory Scheduling - Runahead Execution - Prefetching - Advanced Prefetching - Multiprocessors - Consistency & Coherence - Interconnects - Heterogeneous Multi-Core - Emerging Memory Tech

Lecture 32: Consistency & Coherence

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        Lecture Details

        Lecture 31 Multiprocessor Correctness and Cache Coherence Lecturer Prof. Onur Mutlu (httpusers.ece.cmu.edu~omutlu) Date April 24, 2013. Lecture 31 slides (pdf) httpwww.ece.cmu.edu~ece447s13libexefetch.php?media=onur-447-spring13-lecture31-multiprocessorcorrectnessandcachecoherence-afterlecture.pdf Lecture 31 slides (ppt) httpwww.ece.cmu.edu~ece447s13libexefetch.php?media=onur-447-spring13-lecture31-multiprocessorcorrectnessandcachecoherence-afterlecture.ppt Course webpage httpwww.ece.cmu.edu~ece447s13 Lecture materials httpwww.ece.cmu.edu~ece447s13doku.php?id=schedule

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