Introduction to CAD tools and Technology and modern network synthesis theory – Ultra Dynamic Voltage Scaling : Error Resiliency, Power dissipation and Reliability – Design of Continuous Time Filters – design and synthesis of ladder filters – frequency transformation – signal flow graph – Integrator based realization of ladder filters – Frequency transformation – time domain performance – effect of nonidealities – Sampled Data Filters – basics of sampled data systems – discrete time frequency transformations – basics of switched capacitor filters – Introduction to Switched Capacitor Filters – Data Converters – Design of Switched Capacitor Filters – Design example – signal flow graph and differential architecture – commercial switched capacitor filter in PSoC – Design of Switched Capacitor Filters Continued – Data Converters – performance specifications – ADC and DAC architectures – Flash ADC – Design of High data rate sigma delta ADC – Floor Planning – power supply and grounding – Guard rings and shielding – Introduction to Phase Locked Loop (PLL) – Dynamic of Phase Locked Loop (PLL) – DAC (Digital to Analog Converters) – SAR ADC using parallel charge based DAC and Pipeline ADC – PLL non idealities , design considerations, estimation of capture range and lock range – Delay Locked Loop (DLL) – Examples of Pipeline ADC and Successive Approximation Register (SAR) ADC – Examples on Multi Phases – PLL (Phase Locked Loop) (part 2) – XOR gate as digital phase detector – Basics of PLL dynamics – False Locking – Digital Phase & frequency detector – Scaling – PLL and DLL

Other Resources

Course Curriculum

Introduction to CAD tools and Technology and modern network synthesis theory Details 1:14:5
Ultra Dynamic Voltage Scaling : Error Resiliency, Power dissipation and Reliability Details 1:34:9
Design of Continuous Time Filters (part Details 1:24:38
Design of Continuous Time Filters (part Continued…. Details 1:8:44
Design of Continuous Time Filters (part Details 1:34:34
Sampled Data Filters (Part Details 1:49:52
Sampled Data Filters (part Details 1:26:21
Introduction to Switched Capacitor Filters Details 1:13:25
Data Converters Details 1:22:49
Design of Switched Capacitor Filters Details 1:18:25
Design of Switched Capacitor Filters Continued… Details 1:9:21
Data Converters Details 1:24:42
Design of High data rate sigma delta ADC Details 1:5:54
Floor Planning, power supply and grounding Details 1:29:54
Introduction to Phase Locked Loop (PLL) Details 48:36
Dynamic of Phase Locked Loop (PLL) Details 1:23:58
DAC (Digital to Analog Converters) Details 54:13
SAR ADC using parallel charge based DAC and Pipeline ADC Details 1:20:46
PLL non idealities , design considerations, estimation of capture range and lock range Details 1:23:52
Delay Locked Loop (DLL) Details 1:24:50
Examples of Pipeline ADC and Successive Approximation Register (SAR) ADC Details 1:42
Examples on Multi Phases Details 1:26:22
PLL (Phase Locked Loop) (part , XOR gate as digital phase detector Details 1:16:8
Scaling Details 1:21:41
PLL Phase Locked Loop (part Details 1:19:29
PLL Phase Locked Loop (part and DLL (Delay Locked Loop) Details 1:7:13

This course is delivered by IIT Bombay , as part of NPTEL Free Courses sponsored by Govt of India.

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