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Hardware modeling using verilog

IIT Kharagpur, , Prof. Prof. Indranil Sengupta

Updated On 02 Feb, 19

Overview

The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

Includes

Lecture 1: Lecture 1:

4.1 ( 11 )

Lecture Details

Course Details

COURSE LAYOUT

Week 1: Introduction to digital circuit design flow (3 hours)
Week 2: Verilog variables, operators and language constructs (2 hours)
Week 3: Modeling combinational circuits using Verilog (2 hours)
Week 4: Modeling sequential circuits using Verilog (3 hours)
Week 5: Verilog test benches and design simulation (2 hours)
Week 6: Behavioral versus structural design modeling (2 hours)
Week 7: Miscellaneous modeling issues: pipelining, memory, etc. (2 hours)
Week 8: Processor design using Verilog (4 hours)

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Comments
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Sam

Sep 12, 2018

Excellent course helped me understand topic that i couldn't while attendinfg my college.

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Dembe

March 29, 2019

Great course. Thank you very much.

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