Contents:
Introduction – Introduction of Combinational Circuit Design – Combinational Circuit Design Using MSI Blocks – Combinational Circuit Using Multiple Module – Iterative Circuits – Logic Minimization Tabular Methods – Sequential Circuits: Definitions and Classification – Sequential Circuits: State Equivalance and Minimization – State Machine Synthesis – State Machine Implementation Using Registers & Counters

Multiple State Machine Implementation and Clock Period – Designing with Memories – System Design Case Studies – Asynchronous Sequential Circuit – Asynchronous Sequential Circuit Design – State Assignment in Asynchronous Circuit – Microprogrammed Control – Microprogrammed Control Design – Microsequencer Design

Microprogram Optimization – Microinstruction Optimization – Introduction to VHDL – VHDL Modeling Styles – Behavioral Description in VHDL – Data Flow and Behavioral Modeling – Testing of Digital Circuits – Test Generation Methods – Boolean Difference and D – Algorithm

D – Algorithm – Testing of Sequential Circuits – Signature Analysis & Built – in – Self – Test (BIST) – Multi – Level Logic Synthesis – Low Power Design – Behavioral Synthesis – System Level Design & Modeling

Other Resources

Course Curriculum

lecture 1 – Introduction – I Details 34:41
lecture – 2 Introduction – II Details 36:51
lecture 3 – Review of Combinational Circuit Design Details 39:10
lecture 4 – Combinational Circuit Design Using MSI Blocks Details 46:42
lecture 5 – Combinational Circuit Using Multiple Module Details 40:36
lecture 6 – Iterative Circuits Details 41:31
lecture 7 – Iterative Circuits (contd.) Details 23:33
lecture 8 – Logic Minimization Tabular Methods Details 48:19
lecture 9 – Sequential Circuits: Definitions and Classification Details 43:46
lecture 10 – Sequential Circuits: State Equivalance and Minimization Details 57:6
lecture 11 – State Machine Synthesis Details 41:22
lecture 12 – State Machine Implementation Using Registers & Counters Details 58:58
lecture 13 – Multiple State Machine Implementation and Clock Period Details 50:24
lecture 14 – Designing with Memories Details 44:53
lecture 15 – System Design Case Studies Details 51:23
lecture 16 – Asynchronous Sequential Circuit Details 54:56
lecture 17 – Asynchronous Sequential Circuit Design Details 34:27
lecture 18 – State Assignment in Asynchronous Circuit Details 45:8
lecture 19 – Microprogrammed Control Details 52:16
lecture 20 – Microprogrammed Control Design Details 51:50
lecture 21 – Microsequencer Design Details 48:24
lecture 22 – Microprogram Optimization Details 51:49
lecture 23 – Microinstruction Optimization Details 0:40
lecture 24 – Introduction to VHDL Details 46:43
lecture 25 – VHDL Modeling Styles Details 39:57
lecture 26 – Behavioral Description in VHDL Details 44:23
lecture 27 – Data Flow and Behavioral Modeling Details 35:38
lecture 28 – Testing of Digital Circuits Details 47:51
lecture 29 – Test Generation Methods Details 41:33
lecture 30 – Test Generation Methods (Contd.) Boolean Difference and D – Algorithm Details 32:19
lecture 31 – D – Algorithm Details 41:12
lecture 32 – Testing of Sequential Circuits Details 46:8
lecture 33 – Signature Analysis & Built In Self Test (BIST) Details 26:31
lecture 34 – Multi Level Logic Synthesis Details 32:42
lecture 35 – Low Power Design Details 38:47
lecture 36 – Behavioral Synthesis Details 45:6
lecture 37 – System Level design and modeling Details 46:51

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