Introduction to Digital Circuits – Combinational Logic Basics – Combinatioal Circuits – Logic Simplification – Karnaugh Maps And Implicants – Logic Minimization Using Karnaugh Maps – Karnaugh Map Minimization Using Maxterms – Code Converters – Parity Generator And Display Decoder – Arithmetic Circuits – Cary Look Ahead Adders – Subtractors – 2’s Complement Subtractor And BCD Adder – ARRAY MULTIPLIER – Introduction to Sequential Circuits – S-R,J-K and D Flip Flops – J-K and T Flip Flops – Triggering Mechanisms of Flip Flops and Counters – UP/DOWN COUNTERS – SHIFT REGISTERS – Application of Shift Registers – STATE MACHINES – DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS – DESIGN USING J-K FLIP FLOP – MEALY AND MOORE CIRCUITS – PATTERN DETECTOR – MSI AND LSI BASED DESIGN – MULTIPLEXER BASED DESIGN – Encoders and Decoders – Programmable Logic Devices – Design using Programmable Logic Devices – MSI & LSI based Implementation of Sequential – Design of Circuits Using MSI Sequential Blocks – System Design Example – System Design Using the Concept of Controllers

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Course Curriculum

Introduction to Digital Circuits Details 49:39
Introduction to Digital Circuits II Details 54:28
Combinational Logic Basics Details 49:11
Combinatioal Circuits II Details 53:24
Logic Simplification Details 54:18
Karnaugh Maps And Implicants Details 52:43
Logic Minimization Using Karnaugh Maps Details 52:20
Karnaugh Map Minimization Using Maxterms Details 52:47
Code Converters Details 54:29
Parity Generator And Display Decoder Details 51:27
Arithmetic Circuits Details 52:58
Cary Look Ahead Adders Details 52:41
Subtractors Details 51:1
2’s Complement Subtractor And BCD Adder Details 51:48
ARRAY MULTIPLIER Details 52:57
Introduction to Sequential Circuits Details 50:25
S-R,J-K and D Flip Flops Details 52:53
J-K and T Flip Flops Details 52:44
Triggering Mechanisms of Flip Flops and Counters Details 52:29
UP/DOWN COUNTERS Details 51:34
SHIFT REGISTERS Details 54:36
Application of Shift Registers Details 52:55
STATE MACHINES Details 50:16
DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS Details 53:56
DESIGN USING J-K FLIP FLOP Details 50:56
MEALY AND MOORE CIRCUITS Details 51:6
PATTERN DETECTOR Details 52:45
MSI AND LSI BASED DESIGN Details 47:42
MULTIPLEXER BASED DESIGN Details 49:55
Encoders and Decoders Details 49:45
Programmable Logic Devices Details 52:9
Design using Programmable Logic Devices Details 51:46
Design using Programmable Logic Devices II Details 52:59
MSI & LSI based Implementation of Sequential Details 50:7
MSI and LSI Based Implementation of Sequential II Details 49:40
Design of Circuits Using MSI Sequential Blocks Details 51:26
System Design Example Details 50:58
System Design Example (Contd..) Details 53:23
System Design Using the Concept of Controllers Details 49:46
System Design Using the Concept of Controllers II Details 50:40

This course is part of NPTEL online courses, delivered by IIT Madras.

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