Contents:
Introduction to broadband digital communication,Introduction to broadband digital communication,Serializers and deserializers,Forgot to hit “record”!,CMOS logic, single ended data transmission, limitations,Current mode logic-basic circuit design,Current mode logic-MUX, XOR, latch,Current mode logic-latch design,Current mode logic-latch characteristics,Low pass transmission channel-Intersymbol interference, error rateFirst order channel model, ISI

ISI, jitter, eye opening,Channel characteristics-Intersymbol interference, Crosstalk,Equalizer design,Equalizer design-minimizing the residual error,Equalization-Effect on noise and crosstalk, Tradeoffs between equalization at Tx and Rx; Design of Tx equalizers,Design of Transmit equalizers using flip-flops and transconductors,Tx equalizer-design considerations,Tx equalizer-design considerations; realizing variable coefficients,Differential pair-effect of tail node capacitance; Continuous time equalization,Continuous-time equalizer realization; replica biasing for the tail current source

Assignment 2 discussion,Replica biasing, optimizing transmitter swing,Replica biasing, optimizing transmitter swing,Analog layout optimization; Equalization at the receiver,Equalization at the receiver; Basics of adaptation,LMS adaptation,Sign-sign LMS adaptation,LMS implementation details,Adaptive equalizer implementation, S/H based equalizer, obtaining the gradients,Mid term discussion; Multiplexed and demultiplexed PRBS sequences; Latch vs. amplifier; Zeros for pre- and post- cursor equalization; Echo cancellation,Decision feedback equalizers-elimination of noise enhancement; Error propagation,Decision feedback equalizers-bit error rate,Decision feedback equalizers-implementation issues, Assignment 3 discussion

Decision feedback equalizers-implementation issues,Introduction to clock and data recovery-Frequency multiplication using a phase locked loop,Type I PLL; derivation of the phase model of the PLL; Tri state phase detector,(continued) Type I PLL; derivation of the phase model of the PLL; Tri state phase detector,Type I PLL; Reference feedthrough; Tradeoff between reference feedthrough and lock range,Stability of feedback loops; Derivation of the type II PLL

Realization of type II PLLs-charge pump, loop filter,Reference feedthrough in a type II PLL; Phase detector for random data,Linear phase detector for random data,Linear phase detector; Transfer functions in a PLL,PLL review,Binary phase detectors; bang bang jitter,Miscellaneous topics-Optimal equalizers; Linearity assumption of PLL model; PLL capture phenomenon; Hogge phase detector offset correction

Other Resources

Course Curriculum

lecture1- Introduction to broadband digital communication Details 44:20
lecture2 – Introduction to broadband digital communication Details 31:2
lecture3 – Serializers and Deserializers Details 29:27
lecture4.flv Details 43:39
lecture5 – CMOS logic, single ended data transmission, limitations Details 37:51
lecture6 – Current mode logic – Basic circuit design Details 36:18
lecture7 – Current mode logic – MUX, XOR, Latch Details 32:6
lecture8 – Current mode logic – Latch design Details 28:20
lecture9 – Current mode logic – latch characteristics Details 33:37
lecture10 – Low pass transmission channel – Intersymbol interference, error rate Details 27:42
lecture11 – First order channel model, ISI(Inter Symbol Interference) Details 32:13
lecture12 – Channel characteristics-Intersymbol interference, Crosstalk Details 30:53
lecture13 – Equalizer design Details 28:15
lecture14 – Equalizer design – minimizing the residual error Details 31:56
lecture15 – Equalization – Effect on noise and crosstalk Details 33:59
lecture16 – Tradeoffs between equalization at Transmitter and Receiver Details 26:36
lecture17 – Design of Transmit equalizers using flip-flops and transconductors Details 30:59
lecture18 – Transmitter equalizer – design considerations Details 37:4
lecture19 – Transmitter equalizer – design considerations, realizing variable coefficients Details 37:42
lecture20 – Differential pair – effect of tail node capacitance Details 30:31
lecture21 – Continuous time equalizer realization Details 40:30
lecture22 – Assignment 2 discussion Details 42:29
lecture23 – Replica biasing, optimizing transmitter swing – 1 Details 31:25
lecture24 – Replica biasing, optimizing transmitter swing Details 31:34
lecture25 – Analog layout optimization : Equalization at the receiver Details 37:45
lecture26 – Equalization at the receiver : Basics of adaptation Details 39:34
lecture27 – LMS adaptation Details 33:49
lecture28 – Sign-sign LMS adaptation Details 35:13
lecture29 – LMS implementation details Details 41:39
lecture30 – Adaptive equalizer implementation, Sample/Hold based equalizer Details 38:19
lecture31 – Multiplexed and demultiplexed PRBS sequences,Latch vs. amplifier, Details 41:51
lecture32 – Decision feedback equalizers – elimination of noise enhancement Details 38:37
lecture33 – Decision feedback equalizers – bit error rate Details 35:25
lecture34 – Decision feedback equalizers – implementation issues Details 35:58
lecture35 – Assignment 3 discussion Details 53:31
lecture36 – Decision feedback equalizers – implementation issues Details 50:46
lecture37 – Introduction to clock and data recovery – Frequency multiplication using a PLL Details 38:5
lecture38 – Type 1 PLL; derivation of the phase model of the PLL; Details 49:11
lecture39 – Type 1 PLL, derivation of the phase model of the PLL,Tri state phase detector Details 40:20
lecture40 – Reference feedthrough; Tradeoff between reference feedthrough and lock range Details 53:30
lecture41 – Stability of feedback loops, Derivation of the type II PLL Details 51:52
lecture42 – Realization of type II PLLs – charge pump, loop filter Details 53:50
lecture43 – Reference feedthrough in a type II PLL, Phase detector for random data Details 57:1
lecture44 – Linear phase detector for random data Details 1:1:4
lecture45 – Linear phase detector – Transfer functions in a PLL Details 52:7
lecture46 – PLL review Details 53:51

This course is part of NPTEL online courses, delivered by IIT Madras.

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