Introduction to broadband digital communication,Introduction to broadband digital communication,Serializers and deserializers,Forgot to hit “record”!,CMOS logic, single ended data transmission, limitations,Current mode logic-basic circuit design,Current mode logic-MUX, XOR, latch,Current mode logic-latch design,Current mode logic-latch characteristics,Low pass transmission channel-Intersymbol interference, error rateFirst order channel model, ISI
ISI, jitter, eye opening,Channel characteristics-Intersymbol interference, Crosstalk,Equalizer design,Equalizer design-minimizing the residual error,Equalization-Effect on noise and crosstalk, Tradeoffs between equalization at Tx and Rx; Design of Tx equalizers,Design of Transmit equalizers using flip-flops and transconductors,Tx equalizer-design considerations,Tx equalizer-design considerations; realizing variable coefficients,Differential pair-effect of tail node capacitance; Continuous time equalization,Continuous-time equalizer realization; replica biasing for the tail current source
Assignment 2 discussion,Replica biasing, optimizing transmitter swing,Replica biasing, optimizing transmitter swing,Analog layout optimization; Equalization at the receiver,Equalization at the receiver; Basics of adaptation,LMS adaptation,Sign-sign LMS adaptation,LMS implementation details,Adaptive equalizer implementation, S/H based equalizer, obtaining the gradients,Mid term discussion; Multiplexed and demultiplexed PRBS sequences; Latch vs. amplifier; Zeros for pre- and post- cursor equalization; Echo cancellation,Decision feedback equalizers-elimination of noise enhancement; Error propagation,Decision feedback equalizers-bit error rate,Decision feedback equalizers-implementation issues, Assignment 3 discussion
Decision feedback equalizers-implementation issues,Introduction to clock and data recovery-Frequency multiplication using a phase locked loop,Type I PLL; derivation of the phase model of the PLL; Tri state phase detector,(continued) Type I PLL; derivation of the phase model of the PLL; Tri state phase detector,Type I PLL; Reference feedthrough; Tradeoff between reference feedthrough and lock range,Stability of feedback loops; Derivation of the type II PLL
Realization of type II PLLs-charge pump, loop filter,Reference feedthrough in a type II PLL; Phase detector for random data,Linear phase detector for random data,Linear phase detector; Transfer functions in a PLL,PLL review,Binary phase detectors; bang bang jitter,Miscellaneous topics-Optimal equalizers; Linearity assumption of PLL model; PLL capture phenomenon; Hogge phase detector offset correction
This course is delivered by NPTEL, is part of IIT Madras online courses.
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