# Design Verification and Test of Digital VLSI Circuit

IIT Guwahati Course , Prof. Jatindra Kumar Deka

154 students enrolled

# Overview

Contents:
Introduction : Introduction to Digital VLSI Design Flow - High Level Design Representation - Transformations for High Level Synthesis - Scheduling, Allocation and Binding
Introduction to HLS : Scheduling, Allocation and Binding Problem Scheduling Algorithms,Binding and Allocation Algorithms
.Logic Optimization and Synthesis : Two level Boolean Logic Synthesis - Heuristic Minimization of Two-Level Circuits - Finite State Machine Synthesis - Multilevel Implementation

Verification :
Temporal Logic : Introduction to formal methods for verification - Temporal Logic: Introduction and Basic Operators - Syntax and Semantics of CTL - Equivalence between CTL Formulas
Binary Decision Diagram : Binary Decision Diagram: Introduction and construction - Ordered Binary Decision Diagram - Operations on Ordered Binary Decision Diagram - Ordered Binary Decision Diagram for Sequential Circuits
Verification Techniques : Introduction to Verification Techniques - Model Checking - Symbolic Model Checking

Test :
Introduction to Digital Testing : Introduction to Digital VLSI Testing - Functional and Structural Testing - Fault Equivalence
Fault Simulation and Testability Measures :Fault Simulation - Testability Measures (SCOAP)
Combinational Circuit Test Pattern Generation : Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras - D-Algorithm
Sequential Circuit Testing and Scan Chains : ATPG for Synchronous Sequential Circuits - Scan Chain based Sequential Circuit Testing
Built in Self test (BIST) : Built in Self Test - Memory Testing

### Lecture 2: High Level Design Representation

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# Lecture Details

Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT Guwahati. For more details on NPTEL visit httpnptel.iitm.ac.in

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