CMOS VLSI Design for Power and Speed consideration :Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design – Logical Effort – A way of Designing Fast CMOS Circuits – Power Estimation and Control in CMOS VLSI circuits – Low Power Design Techniques;Datapath Design:Arithmetic Implementation Strategies for VLSI;Interconnect aware design:Interconnect aware design: Impact of scaling, buffer insertion and
Inductive peaking – Interconnect aware design: Low swing and Current mode signaling – Interconnect aware design: Capacitively coupled interconnects;Hardware Description Languages for VLSI Design:Managing concurrency and time in Hardware Description Languages – Introduction to VHDL – Basic Components in VHDL – Structural Description in VHDL – Behavioral Description in VHDL – Introduction to Verilog

FSM Controller/Datapath and Processor Design:FSM + datapath (GCD example) – FSM + datapath (continued) – Single Cycle MMIPS – Multicycle MMIPS – Multicycle MMIPS – FSM;VLSI Design Automation:Brief Overview of Basic VLSI Design Automation Concepts – Netlist and System Partitioning – Timing Analysis in the context of Physical Design Automation – Placement algorithm;VLSI Design Test and Verification:Introduction to VLSI Testing
VLSI Test Basics:VLSI Testing: Automatic Test Pattern Generation,Design for Test (DFT),Built-In Self-Test (BIST) – VLSI Design Verification: An Introduction Equivalence Checking,Equivalence/Model Checking,Model Checking

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Course Curriculum

Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design Details 53:45
Historical Perspective and Future Trends in CMOS VLSI Circuit -Part II Details 1:42:53
Logical Effort – A way of Designing Fast CMOS Circuits Details 1:6:25
Logical Effort – A way of Designing Fast CMOS Circuits continued Details 1:12:51
Logical Effort – A way of Designing Fast CMOS Circuits -Part III Details 1:15:58
Power Estimation and Control in CMOS VLSI circuits Details 1:1
Power Estimation and Control in CMOS VLSI circuits continued Details 1:19:2
Low Power Design Techniques Details 54:28
Low Power Design Techniques -Part II Details 1:51:51
Arithmetic Implementation Strategies for VLSI Details 57:4
Arithmetic Implementation Strategies for VLSI -Part II Details 59:15
Arithmetic Implementation Strategies for VLSI -Part III Details 1:49:15
Arithmetic Implementation Strategies for VLSI -Part IV Details 1:35:43
Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking Details 53:38
Interconnect aware design: Low swing and Current Mod-e signaling Details 53:49
Interconnect aware design: capacitively coupled interconnects Details 49:50
Introduction to Hardware Description Languages Details 51:12
Managing concurrency and time in Hardware Description Languages Details 53:48
Introduction to VHDL Details 52:27
Basic Components in VHDL Details 51:26
Structural Description in VHDL Details 52:54
Behavioral Description in VHDL Details 51:10
Introduction to Verilog Details 55:16
FSM + datapath (GCD example) Details 58:46
FSM + datapath (continued) Details 54:42
Single Cycle MMIPS Details 1:11:28
Multicycle MMIPS Details 1:16:24
Multicycle MMIPS â FSM Details 1:21:43
Brief Overview of Basic VLSI design Automation Concepts Details 1:1:5
Netlist and System Partitioning Details 1:2:49
Timing Analysis in the context of Physical design Automation Details 1:5:22
Placement algorithm Details 48:58
Introduction to VLSI Testing Details 56:9
VLSI Test Basics – I Details 59:39
VLSI Test Basics – II Details 58:16
VLSI Testing: Automatic Test Pattern Generation Details 55:28
VLSI Testing: design for Test (DFT) Details 56:36
VLSI Testing: Built-in Self-Test (BIST) Details 58:14
VLSI design Verification: An Introduction Details 54:21
VLSI design Verification: An Introduction Details 52:31
VLSI design Verification: Equivalence/Model Checking Details 50:21
VLSI design Verification: Model Checking Details 1:26

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