Advanced VLSI Design

IIT Bombay , Prof.A.N. Chandorkar D.K. Sharma Sachin Patkar Virendra Singh

Arithmetic Implementation Strategies for VLSI -Part II

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Lecture Description

Advanced VLSI Design by Prof. A.N. Chandorkar, Prof. D.K. Sharma, Prof. Sachin Patkar, Prof. Virendra Singh,Department of Electrical Engineering,IIT Bombay. For more details on NPTEL visit http://nptel.ac.in

Course Description

CMOS VLSI Design for Power and Speed consideration :Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design – Logical Effort – A way of Designing Fast CMOS Circuits – Power Estimation and Control in CMOS VLSI circuits – Low Power Design Techniques;Datapath Design:Arithmetic Implementation Strategies for VLSI;Interconnect aware design:Interconnect aware design: Impact of scaling, buffer insertion and
Inductive peaking – Interconnect aware design: Low swing and Current mode signaling – Interconnect aware design: Capacitively coupled interconnects;Hardware Description Languages for VLSI Design:Managing concurrency and time in Hardware Description Languages – Introduction to VHDL – Basic Components in VHDL – Structural Description in VHDL – Behavioral Description in VHDL – Introduction to Verilog

FSM Controller/Datapath and Processor Design:FSM + datapath (GCD example) – FSM + datapath (continued) – Single Cycle MMIPS – Multicycle MMIPS – Multicycle MMIPS – FSM;VLSI Design Automation:Brief Overview of Basic VLSI Design Automation Concepts – Netlist and System Partitioning – Timing Analysis in the context of Physical Design Automation – Placement algorithm;VLSI Design Test and Verification:Introduction to VLSI Testing
VLSI Test Basics:VLSI Testing: Automatic Test Pattern Generation,Design for Test (DFT),Built-In Self-Test (BIST) – VLSI Design Verification: An Introduction Equivalence Checking,Equivalence/Model Checking,Model Checking

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