Contents:
Introduction : Introduction to Digital VLSI Design Flow – High Level Design Representation – Transformations for High Level Synthesis – Scheduling, Allocation and Binding
Introduction to HLS : Scheduling, Allocation and Binding Problem Scheduling Algorithms,Binding and Allocation Algorithms
.Logic Optimization and Synthesis : Two level Boolean Logic Synthesis – Heuristic Minimization of Two-Level Circuits – Finite State Machine Synthesis – Multilevel Implementation

Verification :
Temporal Logic : Introduction to formal methods for verification – Temporal Logic: Introduction and Basic Operators – Syntax and Semantics of CTL – Equivalence between CTL Formulas
Binary Decision Diagram : Binary Decision Diagram: Introduction and construction – Ordered Binary Decision Diagram – Operations on Ordered Binary Decision Diagram – Ordered Binary Decision Diagram for Sequential Circuits
Verification Techniques : Introduction to Verification Techniques – Model Checking – Symbolic Model Checking

Test :
Introduction to Digital Testing : Introduction to Digital VLSI Testing – Functional and Structural Testing – Fault Equivalence
Fault Simulation and Testability Measures :Fault Simulation – Testability Measures (SCOAP)
Combinational Circuit Test Pattern Generation : Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras – D-Algorithm
Sequential Circuit Testing and Scan Chains : ATPG for Synchronous Sequential Circuits – Scan Chain based Sequential Circuit Testing
Built in Self test (BIST) : Built in Self Test – Memory Testing

Other Resources

Course Curriculum

Introduction to Digital VLSI Design Flow Details 1:11:21
High Level Design Representation Details 57:35
Transformations for High Level Synthesis Details 57:37
Introduction to HLS: Scheduling, Allocation and Binding Problem Details 1:1:16
Scheduling Algorithms-1 Details 57:38
Scheduling Algorithms-2 Details 1:10:10
Binding and Allocation Algorithms Details 1:7:1
Two level Boolean Logic Synthesis-1 Details 1:8:11
Two level Boolean Logic Synthesis-2 Details 1:4:16
Two level Boolean Logic Synthesis-3 Details 1:23:50
Heuristic Minimization of Two-Level Circuits Details 1:16:37
Finite State Machine Synthesis Details 1:13:42
Multilevel Implementation Details 1:3:52
Introduction to formal methods for design verification Details 53:9
Temporal Logic: Introduction and Basic Operators Details 55:20
Syntax and Semantics of CTL Details 59:34
Syntax and Semantics of CTL — Continued Details 1:8:58
Equivalence between CTL Formulas Details 1:35
Introduction to Model Checking Details 1:2:56
Model Checking Algorithms I Details 55:36
Model Checking Algorithms II Details 56:45
Model Checking with Fairness Details 57:27
Binary Decision Diagram: Introduction and construction Details 1:3:22
Ordered Binary Decision Diagram Details 1:1:43
Operation on Ordered Binary Decision Diagram Details 1:53
Ordered Binary Decision Diagram for State Transition Systems Details 1:1:14
Symbolic Model Checking Details 1:1:51
Introduction to Digital VLSI Testing Details 54:46
Functional and Structural Testing Details 1:21
Fault Equivalence Details 57:13
Fault Simulation-1 Details 52:25
Fault Simulation-2 Details 1:2:11
Fault Simulation-3 Details 1:8:10
Testability Measures (SCOAP) Details 59:51
Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras Details 54:35
D-Algorithm-1 Details 56:43
D-Algorithm-2 Details 1:5:33
ATPG for Synchronous Sequential Circuits Details 1:9:8
Scan Chain based Sequential Circuit Testing-1 Details 52:45
Scan Chain based Sequential Circuit Testing-2 Details 52:11
Built in Self Test-1 Details 59:46
Built in Self Test-2 Details 54:19
Memory Testing-1 Details 57:7
Memory Testing-2 Details 1:12:39

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